PROJECT: ip_gddr71rx
		working_path: "D:/RD_Work_Area/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/syn_results"
		module: ip_gddr71rx
		verilog_file_list: "C:/lscc/diamond/3.3_x64/cae_library/synthesis/verilog/ecp5um.v" "C:/lscc/diamond/3.3_x64/cae_library/synthesis/verilog/pmi_def.v" "D:/RD_Work_Area/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v"
		vlog_std_v2001: true
		constraint_file_name: "D:/RD_Work_Area/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.fdc"
		suffix_name: edn
		output_file_name: ip_gddr71rx
		write_prf: true
		disable_io_insertion: true
		force_gsr: false
		frequency: 100
		fanout_limit: 50
		retiming: false
		pipe: false
		part: LFE5UM-85F
		speed_grade: 8
		
